Achronix Speedster22i Clock and Reset Networks User Manual Page 27
- Page / 28
- Table of contents
- BOOKMARKS
- Speedster22i Clock and 1
- Reset Networks 1
- User Guide 1
- Copyright Info 2
- Table of Contents 3
- Introduction 4
- Reset Resource Counts 5
- Clock Sources 6
- Reset Sources 6
- Core Clock Network 7
- Direct Core Clock Network 8
- Clock Generator (CG) 10
- Phase Locked Loop (PLL) 11
- 12 UG027, May 21, 2014 12
- UG027, May 21, 2014 13
- Clock Mux 14
- Clock Hub 15
- Clock Region 16
- Clk Div & 18
- Junctions 19
- West-North (WN) IO Cluster 20
- Boundary Clock Network 21
- 22 UG027, May 21, 2014 22
- Clock Setting and Reporting 23
- FPGA Core 24
- Reset Distribution 26
- Revision History 28
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